3. Dividing a Double-Word Dividend

This example contains the code sequence to divide a 64-bit signed dividend by a 32-bit signed divisor using the DS (Divide Step) instruction. Table 7-1 “Register Designations ” lists the registers that this program uses.

start
              MOVB,>=         dvdu,rem,check_mag  ; Move upper dividend
                                                  ;   check for &< 0
              ADD             0,dvdl,quo          ; Move lower dividend always
              SUB             0,quo,quo           ; Get absolute value of
              SUBB            0,rem,rem           ;   the dividend in rem,quo
check_mag
              SUBT,=          0,dvr,tp            ; Check 0, clear carry,
                                                  ;   negate the divisor
                                                  ;   and trap if dvr = 0
              DS              0,tp,0;             ; Set V-bit to the complement
                                                  ;   of the divisor sign
              ADD             quo,quo,quo         ; Shift msb bit into carry
              DS,&<<           rem,dvr,rem         ; 1st divide step, if carry
                                                  ;   out msb of quotient = 0
              B,n             min_ovfl            ; Abs(quotient) > 2**31
                                                  ;   deal with elsewhere
              ADDC            quo,quo,quo         ; Shift quo with/into carry
              DS              rem,dvr,rem         ; 2nd divide step
              ; ...
              ;repeat divide step sequence
              ; ...
              ADDC            quo,quo,quo         ; Shift quo with/into carry
              DS              rem,dvr,rem         ; 31st divide step
              ADDC            quo,quo,quo         ; Shift quo with/into carry
              DS              rem,dvr,rem         ; 32nd divide step,
              ADDC            quo,quo,quo         ; Shift last quo bit into quo
              ADDB,>=,n       rem,0,finish        ; Branch if pos. rem
              ADD,&<           dvr,0,0             ; If dvr > 0, add dvr
              ADD,tr          rem,dvr,rem         ;   for correcting rem.
              ADDL            rem,tp,rem          ; Else add absolute value dvr
finish
              ADD,>=          dvdu,0,0            ; Set sign of rem
              SUB             0,rem,rem           ;   to sign of dividend
              XOR,>=          dvdu,dvr,0          ; Get correct sign of quo
              SUB             0,quo,quo           ;   based on operand signs

Table 7-1 Register Designations

Register Designations	Purpose
`dvr`	Register holding divisor.
`dvdu dvd1`	Pair of registers holding dividend.
`tp`	Temporary register.
`quo`	Register holding quotient.
`rem`	Register holding remainder.

3. Dividing a Double-Word Dividend

Technical documentation

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