HP-UX Memory Management: White Paper

List of Figures

1-1 Physical memory available to processes

1-2 Major sections of system address space.

1-3 Bit layout of physical address

1-4 Bit layout of virtual page address

1-5 Processor architecture, showing major components

1-6 Role of the TLB.

1-7 The TLB is a cache for address translations

1-8 Every cache entry consists of a cache tag and cache line.

1-9 PPNs from Cache and TLB are compared

1-10 Virtual address translation

1-11 Access control to virtual pages

1-12 Summary of page retrieval from TLB, Cache, PDIR

1-13 Memory management structures

1-14 Virtual memory elements of the pregion

1-15 Mapping the pseudo-vas structures

1-16 A chunk contains 32 vfddbd (256 bytes)

1-17 Virtual frame descriptor (vfd) contents

1-18 Contents of disk block descriptor (dbd)

1-19 A sample B-tree (order = 3, depth = 3)

1-20 Contents of the htbl index

1-21 Mapping from the htbl entry to the page directory entry

1-22 How multiple addresses hash to the same HTBL entry

1-23 Physical-to-virtual address translation

1-24 Available memory in the system

1-25 Two-handed vhand clock algorithm, showing also the factors that affect vhand

1-26 Ranges within which pregion pages are aged and stolen

1-27 sched() chooses processes to deactivate based on size, nice priority, and how long it has been running.

1-28 Reserving swap space from file-system swap to memory

1-29 Choosing a swap location

1-30 The swaptab and swapmap structures

1-31 Duplicating pregions with shared regions

1-32 Duplicating a child process of type RT_PRIVATE

1-33 The first time a read is done to a copy-on-write page

1-34 Checking the free list to fault in a DBD_FSTORE page

1-35 DBD_FSTORE fault of data not in the free list