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MAPPING VIRTUAL TO PHYSICAL MEMORY

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The PA-RISC hardware attempts to convert a virtual address to a physical address with the TLB or the block TLB. If it cannot resolve the address, it generates a page fault (interrupt type 6 for an instruction TLB miss fault; interrupt type 15 for a data TLB miss fault). The kernel must then handle this fault.

PA-RISC uses a hashed page table (HTBL) to pinpoint an address in the enormous virtual address space. A ratio is kept of PDIR to hash table entries, depending on specific PA-RISC implementation (see cpu.h). Control register 25 (CR25) contains the hash table address (see reg.h).

Figure 1-20 Contents of the htbl index

[Contents of the htbl index]

The HTBL

The algorithm for converting a virtual address to a physical address depends on the particular processor.

Likewise, the algorithm for choosing the size of HTBL has been developed empirically as the result of performance tests.

  • Each graphics driver estimates how many entries it will need for I/O mapping. This number is stored in niopdir.

  • The kernel first approximates nhtbl as the sum of niopdir and the number of pages of RAM (physmem).

  • nhtbl is now adjusted to a power of two and rounded appropriately.

Figure 1-21 Mapping from the htbl entry to the page directory entry

[Mapping from the htbl entry to the page directory entry]

The index generated by the hashing algorithm is now used as an index into HTBL. Each entry in the table is referred to as a pde (page directory entry), and is of type struct hpde.

The virtual space and offset are compared to information in the pde to verify the entry. The physical address is retrieved from the pde to complete the translation from virtual address to physical address.

When multiple addresses hash to the same HTBL entry

As with any hash algorithm, multiple addresses can map to the same HTBL index. The entry in HTBL is actually the starting point for a linked list of pdes. Each entry has a pde_next pointer that points to another pde, or contains NULL if it is the last item of the linked list.

Each HTBL entry can point to two other collections of pdes, ranging from base_pdir to htbl and from pdir (which is also the end of HTBL) to max_pdir. The entirety of the HTBL and surrounding pdes is referred to collectively as the sparse PDIR. HTBL is always aligned to begin at an address that is a multiple of its size (that is, a multiple of nhtbl * sizeof(struct hpde)).

In practice, HTBL contains sufficient entries, as that the linked lists seldom grow beyond three links. pdir_free_list points to a linked list of sparse PDIR entries that are not being used and are available for use. pdir_free_list_tail points to the last pde on that linked list.

Figure 1-22 How multiple addresses hash to the same HTBL entry

[How multiple addresses hash to the same HTBL entry]

Mapping Physical to Virtual Addresses

HP-UX uses a hashed page directory to translate from virtual to physical address.

The pfdat table maps physical to virtual addresses. Inverse translations from physical to virtual use the pfn_to_virt_table[], an array that contains entries of either space and offset page (in the case of a single translation to a page) or a list of alias structures (when the physical page has more than one virtual address translation).

The hashed pdir stores the physical address in the translation "bucket" (hash table) to disassociate the physical page number from that page's pde.

Figure 1-23 Physical-to-virtual address translation

[Physical-to-virtual address translation]

The pfn_to_virt_table may contain the space.offset (virtual address) corresponding to a physical address or it may have a pointer to a link list of alias structures, each of which has a space.offset pair.

Address Aliasing

HP-UX supports software address aliasing for text only of EXEC_MAGIC executables. (Whereas the hardware implements address aliasing on 1MB boundaries, software address aliasing is implemented on a per-page basis; pages are 4KB apart.)

When a text segment is first translated, it has no alias. However, if a process or thread attaches to the same text segment, it may require another translation. Processes sharing text segments do not use aliases. Only processes with private text segments that share data pages using copy-on-write use aliases.

When multiple virtual addresses translate to the same physical address, HP-UX uses alias structures to keep track of them. Aliases for a page frame (pfn) are maintained via alias chains off the pfn_to_virt_table[]. When a pfn_to_virt_table's space field is invalid and the offset field is non-zero, the non-zero value points to the beginning of a linked list of alias structures. Each alias structure contains the space and offset of the alias, and a temporary hold field for a pde's access rights and access ID. The pfdat_lock of the alias's pfn protects the alias chain from being read and modified.

To locate the pde for a particular alias space and offset, the space and offset are hashed for the pde chain and its corresponding pdlock. Once the pdlock is obtained, the vtopde() routine walks the pde hash chain to find a match of the tag.

The aa_entfreelist is the head of the doubly-linked list of free alias entries. The system gets an alias structure from aa_entfreelist, in which it stores the information for this new virtual-to-physical translation.

The global variable max_aapdir contains the total number of alias pdes on the system. Once a page is allocated for use as alias pdes, it is not returned, so the value of max_aapdir may grow over time but will never shrink.

The number of available alias pdes is stored in aa_pdircnt. When an alias pde is used or reserved (we reserve one if we include an HTBL pde in an alias linked list, in case we have to move it later), aa_pdircnt is decremented. When an alias pde is returned to aa_pdirfreelist or unreserved, aa_pdircnt is incremented.

The number of available alias structures is kept in aa_entcnt. Once a page is allocated for use as a group of alias structures, it is not returned. We do not keep track of the total number of alias structures on the system, just the number of available structures.