HP 3000 Manuals HP 3000 Manuals
MR
Modifies the contents of the specified CM or NM register.
Syntax
MR cm_register [newvalue]
MR nm_register [newvalue]
By default, the current register value is displayed. The ENV variable
QUIET_MODIFY can be used to suppress the display of the current value.
Parameters
cm_register The CM register whose contents are to be modified. This
can be:
DB The stack base relative word offset of DB.
DBDST The DB data segment number.
CIR The current instruction register.
CMPC The full logical CM program counter address.
* Only the offset part can be modified.
* CIR will also be modified.
Q The Q register word offset, DB relative.
S The S register word offset, DB relative.
SDST The stack data segment number.
STATUS The CM status register.
* The segment number portion cannot be
modified.
X The X (index) register.
NOTE CM registers can not be modified when the user initially entered
Debug in NM (nmdebug).
nm_register The NM register whose contents are to be modified.
NOTE NM registers can not be modified when the user initially entered
Debug in CM (cmdebug).
Modifying PC modifies PCOF and PCSF. It sets PCOB to PCOF+4 and to
PCSF. The original priv bits are retained. That is, when PC is
modified, the priv bits are unaffected.
To fully understand the use and conventions for the
various registers, refer to the Precision Architecture
and Instruction Reference Manual(09740-90014) and
Procedure Calling Conventions Reference Manual
(09740-90015). (These may be ordered as a set with Part
Number 09740-64003.) The procedure calling conventions
manual is of particular importance for understanding how
the language compilers utilize the registers to pass
parameters, return values, and hold temporary values.
The following tables list the NM registers available
within System Debug. Many registers have aliases
through which they may be referenced. Alias names in
italics are not available in System Debug.
Access rights abbreviations are listed below. PM
indicates that privileged mode (PM) capability is
required.
d Display access
D PM display access
m Modify access
M PM modify access
The following registers are known as the General
Registers.
Name Alias Access Description
---------------------------------------------------------------------------------------
RO none d A constant 0
R1 none dm General register 1
R2 none dm Used to hold RP at
times
R3 none dm General register 3
:
R22 none dm General register 22
R23 ARG3 dm Argument register 3
R24 ARG2 dm Argument register 2
R25 ARG1 dm Argument register 1
R26 ARG0 dm Argument register 0
R27 DP dM Global data pointer
R28 RET1 dm Return register 1
R29 RET0 dm Return register 0
SL dm Static link
R30 SP dM Current stack pointer
R31 MRP dm Millicode return
pointer
The following registers are pseudo registers. They are
not defined in the Precision Architecture, but are terms
used in the Procedure Calling Conventions document and
by the language compilers. They are provided for
convenience. They are computed based on stack unwind
information. They may not be modified.
Name Alias Access Description
---------------------------------------------------------------------------------------
RP none d Return pointer (not
the same as R2)
PSP none d Previous stack
pointer
The following registers are known as the Space
Registers. They are used for short pointer addressing:
Name Alias Access Description
---------------------------------------------------------------------------------------
SR0 none dm Space register 0
SR1 SARG dm Space register
argument
SRET dm Space return register
SR2 none dm Space register 2
SR3 none dm Space register 3
SR4 none dM Process local code
space(tracks PC
space)
SR5 none dM Process local data
space
SR6 none dM Operating system data
space 1
SR7 none dM Operating system data
space 2
The following registers are known as the Control
Registers. They contain system state information:
Name Alias Access Description
---------------------------------------------------------------------------------------
CR0 RCTR dM Recovery counter
CR8 PID1 dM Protection ID 1 (16
bits)
CR9 PID2 dM Protection ID 2 (16
bits)
CR10 CCR dM Coprocessor
configuration (8
bits)
CR11 SAR dm Shift amount register
(5 bits)
CR12 PID3 dM Protection ID 3 (16
bits)
CR13 PID4 dM Protection ID 4 (16
bits)
CR14 IVA dM Interrupt vector
address
CR15 EIEM dM External interrupt
enable mask
CR16 ITMR dM Interval timer
CR17 PCSF dM PC space queue front
none PCSB dM PC space queue back
CR18 PCOF dM PC offset queue front
none PCSB dM PC offset queue Back
none PCQF dM PC queue (PCOF.PCSF)
front
none PCQB dM PC queue (PCOB.PCSB)
back
none PC dM PCQF with priv bits
set to zero
none PRIV dM Low two order bits
(30,31) of PCOF.
CR19 IIR dM Interrupt instruction
register
CR20 ISR dM Interrupt space
register
CR21 IOR dM Interrupt offset
register
CR22 IPSW dM Interrupt processor
status word
PSW dM Processor status word
CR23 EIRR dM External interrupt
request register
CR24 TR0 dM Temporary register 0
:
CR31 TR7 dM Temporary register 7
_______________________________________________________
NOTE the Precision Architecture and Instruction
Reference Manual (09740-90014) refers to the PC
(program counter) registers as the IA (instruction
address) registers. This manual will use the PC
mnemonic when referring to the IA registers.
_______________________________________________________
The following registers are floating-point registers.
If a machine has a floating-point coprocessor board,
these values are from that board. If no floating-point
hardware is present, the operating system emulates the
function of the hardware, in which case these are the
values from floating-point emulation.
Name Alias Access Description
---------------------------------------------------------------------------------------
FP0 none dm FP register 0
FP1 none dm FP register 1
FP2 none dm FP register 2
FP3 none dm FP register 3
FP4 FARG0 dm FP argument register
0
FRET dm FP return register
FP5 FARG1 dm FP argument register
1
FP6 FARG2 dm FP argument register
2
FP7 FARG3 dm FP argument register
3
FP8 none dm FP register 8
:
FP15 none dm FP register 15
FPSTATUS none dm FP status reg (left
half of FP0)
FPE1 none dm FP exception reg 1
(right half of FP0)
FPE2 none dm FP exception reg 2
(left half of FP1)
FPE3 none dm FP exception reg 3
(right half of FP1)
FPE4 none dm FP exception reg 4
(left half of FP2)
FPE5 none dm FP exception reg 5
(right half of FP2)
FPE6 none dm FP exception reg 6
(left half of FP3)
FPE7 none dm FP exception reg 7
(right half of FP3)
newvalue The new value for the register can optionally be
supplied on the command line. If the new value was
omitted, Debug displays the old value, and prompts for
the new value. To retain the original value, just hit
return.
When a register is modified, the actual machine
registers are not changed until the process is resumed.
That is, the new value is recorded and takes effect when
Debug is exited using the CONTINUE or EXIT commands.
Furthermore the value is applied only to the PIN being
debugged. This is true of all but several special
registers that are expected to remain constant during
the life of MPE XL. The list of these registers follows:
sR6
sR7
tr0-tr7 Alias for cr24 - cr31
cCr Alias for cr10
iVa Alias for cr14
eIem Alias for cr15
eIrr Alias for cr23
When one of these registers is modified, the new value
takes effect immediately. Since these registers are
global across all processes, all other users are
affected by the change.
Examples
%cmdebug > mr cmpc
CMPC=PROG %0.01754 := prog(0.1762)
Modify the contents of the CM program counter. Only the offset portion
of the CM logical address can be modified. It is not possible to change
the logical segment number portion.
Note that this also modifies CIR, the current instruction register.
%cmdebug > mr x 0
X=000123 := 0
Zero the X register.
$nmdebug > mr pc pc + 4
pc=0021d7b4 := 0021d7b8
Advance the PC (this changes pcq front and pcq back).
$nmdebug > mr ret0 [psp-20]
r28=00000001 := 00ef2340
Modify return register 0 (r28) to be the contents of the address
specified by psp-20.
Limitations, Restrictions
The PC register can not be modified unless the user has privileged mode.
When CM code has been translated, and is executing translated,
modification of the CM registers may result in an undefined/undesirable
state.
Refer to appendix C for a discussion of CM object code translation, node
points, and breakpoints in translated CM code.
CAUTION The output format of all System Debug commands is subject to
change without notice. Programs that are developed to
postprocess System Debug output should not depend on the exact
format (spacing, alignment, number of lines, uppercase or
lowercase, or spelling) of any System Debug command output.