HP 3000 Manuals

General Information Manual

A Closer Look at HP PA-RISC 

Additional information about PA-RISC is provided below.  For more
details, please refer to the HP Precision Architecture Data Sheet. 

Instruction set 

PA-RISC defines 140 instructions.  Each instruction is 32 bits long and
has a fixed format.  To minimize complexity and to enable the machine to
be cycled as quickly as possible, the instruction set directly supports
only simple functions.  Nonetheless, some of the PA-RISC instructions
provide functions that typically would require multiple instructions on
conventional systems.  For example, the add and branch instruction
performs a calculation and a conditional branch in a single cycle.  Such
a function on conventional systems typically requires multiple
instructions.

Floating-point instructions 

Floating-point calculations are specified by compilers for any high-level
language variables declared by the programmer as real numbers.  In
particular, engineering, scientific, and statistical applications often
use floating-point data types.  PA-RISC supports single-precision
(32-bit), double-precision (64-bit), and quadruple-precision (128-bit)
arithmetic operations.  Floating-point calculations can be performed in
software by a sequence of integer calculations and conversions, but they
can be executed much faster by the floating-point coprocessor hardware.
With a floating-point coprocessor, floating-point calculations can be
performed while the CPU continues to execute in parallel, thus allowing
PA-RISC to provide high performance for applications that use
floating-point calculations.

Data types 

PA-RISC supports 16- and 32-bit integers, either signed or unsigned.
Characters are stored as 8-bit quantities, conforming to the ASCII
standard for values 0 through 127 and HP's 8-bit extended Roman 8
character set for values 128 through 255.  PA-RISC supports both packed
and unpacked decimal data representations.  Single, double, and
quadruple-word floating-point operands are represented in accordance with
the ANSI/IEEE 754-1985 standard.

CPU register set 

There are 32 available general-purpose registers, each 32 bits wide, for
holding operands and results of processor computations.  Additionally, a
total of 32 control and status registers are available in the CPU for
interrupt processing, virtual memory access protection, and other system
functions.  CPU status is maintained in the 32-bit processor status word
(PSW), which reflects the state of key CPU flags and status bits.

Two CPU registers are used to point to the next instruction to be
executed.  The instruction address space register (IA Space) points to
the 4-Gbyte space that holds the next instruction.  The instruction
address offset register (IA Offset) points to the location within that
space that holds the instruction.

Virtual memory 

Virtual memory allows the programmer to use a memory space that is
actually many times larger than the physical memory installed in the
system.  The advantage of a virtual memory scheme is that a programmer
generally does not have to be concerned about program or data size
limitations in available memory space.  The huge virtual address space
available on the 900 Series systems is fully supported by the operating
system.

Virtual memory is organized as a set of more than four billion linear
regions divided into over 65,000 spaces, with each space 4 Gbytes in
length.  Spaces are further divided into fixed-length, 2-Kbyte pages,
which can hold code, data, or both.  Space registers hold either 16 bits
(for 48-bit addressing) or 32 bits (for 64-bit addressing), and they are
used to point to the virtual space to be accessed.  The specific location
within a space is specified by a 32-bit quantity called the byte offset.
With eight space registers available in the CPU, multiple spaces can be
supported simultaneously.


          Figure A-6.  Virtual Memory Organization 

Virtual address translation 

The 48-bit or 64-bit virtual address generated by the processor must be
translated into a physical address that will be transmitted to physical
memory to access the desired code or data.  Virtual addresses are
translated to physical addresses by the translation lookaside buffer
(TLB) hardware in the processor.  Conceptually, the TLB can be thought of
as a table containing translations for recently accessed virtual pages.


          Figure A-7.  Virtual Address Translation 

Virtual memory access protection 

The TLB hardware supports protection mechanisms to ensure that the
currently executing process can perform only the code, data, or I/O
accesses for which it is authorized.  Included in the access-checking
mechanisms are four privilege levels.  Protection parameters associated
with each page define the privilege level required to access that page
and the types of accesses permitted.  For each requested access, these
privilege parameters are checked against the privilege level of the
currently executing process to ensure that the process has sufficient
authorization to perform that access.  Additionally, within each
protection access level, there is a 15-bit protection identifier
associated with each page.  This identifier, maintained by the operating
system and checked by the TLB hardware, provides the flexibility for data
and code sharing while providing a high level of protection against
unauthorized accesses.

MPE/iX 5.0 Documentation