HP 3000 Manuals HP 3000 Manuals
RISC Attributes: Maximizing Processor Performance The 900 Series systems are the first business computing systems that are true RISC systems. RISC actually goes far beyond simply implementing a reduced number of instructions. There are actually several key RISC attributes, and each of them is discussed below. Note that the 900 Series systems adhere to all of these principles. Hardwired control and single-cycle execution The goal with RISC systems is to perform the simple, often-executed functions as quickly as possible. Unlike conventional systems, which utilize a microcoded control store, typically require several machine cycles to execute even the simplest instructions. RISC instructions are executed directly by hardware in a single CPU cycle. More complex functions, which are often supported directly in the instruction sets of conventional systems, are performed using a sequence of simple instructions generated by high-level language compilers. Reduced number of instructions So that the machine can be cycled as quickly as possible, RISC systems support a reduced number of instructions and fewer addressing modes than typical systems. For example, typical complex architectures may use more than 300 instructions plus a large number of addressing modes; in comparison, 140 simple instructions are provided with PA-RISC systems. This reduced complexity allows the instruction decoding and control circuitry to be simplified, resulting in lower cost and higher performance. Fixed instruction length and format All instructions defined in the PA-RISC instruction set are fixed-length, 32-bit instructions. A fixed instruction length helps facilitate the simultaneous execution of multiple instructions, a capability known as instruction pipelining. Furthermore, all instructions are fixed format, which means that the instruction opcode and the operand registers are always specified in the same place in each instruction. Having fixed-format instructions allows instruction decoding and fetching of required operands to occur in parallel, thus increasing processor efficiency and performance. Register-intensive operation Calculations are performed only on operands held in high-speed, general-purpose registers in the CPU, so calculations are not slowed down by accesses to relatively slow cache or main memory. With a relatively large number (32) of these high-speed registers available, it is possible for compilers to produce and arrange instructions such that operands can be reused as often as possible, again minimizing the number of accesses to slower cache storage and main memory. Furthermore, register-intensive operation allows for simplified data and control paths, which simplifies pipeline design and helps minimize the CPU cycle time. Load/Store memory To minimize processor complexity and reduce CPU cycle time, only load and store instructions access memory. Since load instructions access storage that is relatively slow compared to CPU registers, these instructions take longer to execute. So that the CPU cycle time does not have to be increased because of these instructions, they are implemented in multiple cycles. However, the compilers schedule instructions so that multicycle load instructions are overlapped with other processing, thus allowing the effective execution rate to still approach one instruction per cycle. Decreased effort atrun time With a reduced-complexity system, a fundamental principle is to shift the burden of complexity from the processor to the high-level language compilers. With a large degree of complexity in the processor, conventional systems pay a performance penalty each time a program is run. With a reduced-complexity system, complexity and effort are shifted to compile time, so that any penalties for having a more sophisticated compiler are paid only once, when the program is compiled. In this way, object code can be streamlined and optimized for performance and the program can be run as quickly as possible.