HP 3000 Manuals HP 3000 Manuals
Chapter 5 Optimizing a Program The Optimizer is a program that is an integrated part of an MPE/iX compiler. It is available to use with HP C/iX, HP COBOL II/XL, HP FORTRAN 77/iX, and HP Pascal/iX. When you compile a program, you can select an optimizer option that will use the MPE/iX Optimizer to improve the code. This chapter provides an overview of: * Techniques a programmer can use to program for best optimization. * How Optimizer aids in producing improved code. For detailed information on how each compiler optimizes and actions necessary when an optimized program fails, refer to the following manuals in the Language Series: * HP C/iX Reference Manual Supplement (31506-90001). * HP COBOL II/XL Programmer's Guide (31500-90002). * HP FORTRAN 77/iX Programmer's Guide Supplement (31501-90002). * HP Pascal/iX Programmer's Guide (31502-90002).
NOTE Symbolic debugging is not available when the optimizer option is selected.
The MPE/iX Optimizer can help a program take full advantage of the 900 Series HP Precision Architecture (HP-PA) in the following ways: * The small instruction set and pipeline architecture allows concurrent execution of multiple instructions. Thus, improved program execution speed can be achieved by using careful instruction scheduling. * Many registers are available in the CPU for fast memory referencing. The Optimizer may promote frequently used variables to reside in registers instead of in memory. On the 900 Series, you can optimize at a level lower than that which is expedient with most commercial optimizers: at compile time, at the machine instruction level, after instruction selection. * The Optimizer may move loop-invariant instructions out of program loops, eliminate redundant calculations, and eliminate unnecessary memory references. Efficient instruction scheduling avoids hardware interlocks and eliminates branch delay slots, fully utilizing fast instruction cycle time of the 900 Series. Hardware interlock occurs when two pipelined instructions both require the same resource or when one instruction requires a result of a previous instruction that has not completed. With a graph of program flow to reveal instruction dependencies, instruction scheduling can attempt to avoid hardware interlocks. On the 900 Series, a branch does not take effect until the second machine cycle after the branch instruction. The instruction immediately after a branch instruction is called the delay slot. Even when you do not select optimization, the compiler tries to schedule a useful instruction in the delay slot. However, the MPE/iX Optimizer does a better job of branch delay scheduling and may be able to completely eliminate some branches.